Detection of residual liner materials after polishing in damascene process

ABSTRACT

A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. application Ser. No. 10/904,329filed Nov. 4, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The embodiments of the invention generally relate to integrated circuitmanufacturing, and more particularly to techniques for identifyingdefects in integrated circuits during manufacturing.

2. Description of the Related Art

Damascene processing typically involves the deposition of liner filmsbetween metal and insulating layers. These liner films should generallybe completely removed in non-damascene areas in a subsequent chemicalmechanical polishing (CMP) process. However, the CMP process typicallydoes not adequately remove all of the liner material due to the localtopography from circuit pattern factors and defects, which are bothcompounded by the general non-uniformity of the CMP process.

Usually, the residual liner films in between the metal layers in anintegrated circuit device cannot be detected during standard inspectionsthereby causing metal shorting of various structures in the device,which cause significant major yield loss and reliability failure of thedevice. Undoubtedly, it would be quite advantageous if the residualliner films were easily detectable during a subsequent inspectionprocess. However, typical residual films appear transparent when viewedby optical inspection. Thus, they generally cannot be detected byroutine optical inspection. Therefore, there remains a need for a noveltechnique that allows for easier and more precise inspections ofdamascene structures.

SUMMARY OF THE INVENTION

In view of the foregoing, an embodiment of the invention provides anintegrated circuit comprising a substrate; a dielectric layer over andadjacent to the substrate; a marker layer over and adjacent to thedielectric layer; a liner over and adjacent to the marker layer; and ametal layer over and adjacent to the liner, wherein the marker layercomprises an ultraviolet detectable material, which upon excitation byan ultraviolet ray signals an absence of the metal layer and the linerover the marker layer. Moreover, the marker layer comprises a separatelayer from the dielectric layer. Additionally, the ultravioletdetectable material comprises fluorescent material or phosphorescentmaterial.

Another embodiment of the invention provides a method of detectingwhether post-CMP (chemical mechanical polishing) defects exist in anintegrated circuit, wherein the method comprises depositing a dielectriclayer over a substrate; forming a marker layer over the dielectriclayer, wherein the marker layer comprises an ultraviolet detectablematerial; patterning the marker layer and the dielectric layer therebycreating exposed portions of the dielectric layer; depositing a linerover the marker layer and the exposed portions of the dielectric layer;depositing a metal layer over the liner; polishing the metal layer andthe liner; and exposing the marker layer to an ultraviolet ray, whereindetection of the ultraviolet detectable material by the ultraviolet raysignals an absence of the metal layer and the liner over the markerlayer. The method further comprises configuring the marker layer as aseparate layer from the dielectric layer. In the step of forming, theultraviolet detectable material comprises fluorescent material orphosphorescent material. Additionally, the method further comprisesre-polishing the liner upon non-detection of the ultraviolet detectablematerial by the ultraviolet ray. Furthermore, the marker layer signalsan endpoint for CMP processing during fabrication of the integratedcircuit. The method further comprises analyzing polishing slurryeffluent generated from the polishing process for a presence/absence ofthe ultraviolet detectable material, wherein detection/non-detection ofthe ultraviolet detectable material in the polishing slurry effluentsignals an endpoint for CMP processing during fabrication of theintegrated circuit.

Another aspect of the invention provides a method of detecting whetherpost-CMP (chemical mechanical polishing) defects exist in an integratedcircuit, wherein the method comprises depositing a dielectric layer overa substrate; forming a marker layer comprising an ultraviolet detectablematerial over the dielectric layer; patterning the marker layer and thedielectric layer thereby creating exposed portions of the dielectriclayer; depositing a liner over the marker layer and the exposed portionsof the dielectric layer; depositing a metal layer over the liner; andpolishing the metal layer and liner and the marker layer. The methodfurther comprises exposing the dielectric layer to an ultraviolet light;and detecting whether the liner and the marker layer are present overthe dielectric layer, wherein detection of the ultraviolet detectablematerial by the ultraviolet light signals a presence of the liner andthe marker layer over the dielectric layer. Moreover, the method furthercomprises configuring the marker layer as a separate layer from thedielectric layer. In the step of forming, the ultraviolet detectablematerial comprises fluorescent material or phosphorescent material.Additionally, the method further comprises re-polishing the liner andthe marker layer upon detection of the ultraviolet detectable materialby the ultraviolet light; and analyzing polishing slurry effluentgenerated from the polishing process for a presence/absence of theultraviolet detectable material, wherein detection/non-detection of theultraviolet detectable material in the polishing slurry effluent signalsan endpoint for CMP processing during fabrication of the integratedcircuit.

The advantages afforded by the embodiments of the invention includeimproved process yield, performance, and reliability. Moreover, theembodiments of the invention also provide a low-cost improvement, whichmay reduce overall processing time by limiting the number of rework orCMP “touch-up” steps. By monitoring the CMP slurry for lack of markermaterial after the marker material is first detected, overpolishing ofthe damascene lines (which would result in higher resistance wires) canalso be reduced.

These and other aspects of the embodiments of the invention will bebetter appreciated and understood when considered in conjunction withthe following description and the accompanying drawings. It should beunderstood, however, that the following descriptions, while indicatingpreferred embodiments of the invention and numerous specific detailsthereof, are given by way of illustration and not of limitation. Manychanges and modifications may be made within the scope of theembodiments of the invention without departing from the spirit thereof,and the embodiments of the invention include all such modifications.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the invention will be better understood from thefollowing detailed description with reference to the drawings, in which:

FIG. 1 is a schematic diagram of a partially completed integratedcircuit according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a partially completed integratedcircuit following dual-damascene patterning according to an embodimentof the invention;

FIG. 3 is a schematic diagram of a partially completed integratedcircuit following liner deposition according to an embodiment of theinvention;

FIG. 4 is a schematic diagram of a partially completed integratedcircuit following metallization deposition according to an embodiment ofthe invention;

FIG. 5 is a schematic diagram of a partially completed integratedcircuit following polishing according to a first embodiment of theinvention;

FIG. 6 is a schematic diagram of a partially completed integratedcircuit being exposed to ultraviolet rays according to a firstembodiment of the invention;

FIG. 7 is a flow diagram illustrating a preferred method according to afirst embodiment of the invention;

FIG. 8 is a schematic diagram of a partially completed integratedcircuit following polishing according to a second embodiment of theinvention;

FIG. 9 is a schematic diagram of a partially completed integratedcircuit being exposed to ultraviolet light according to a secondembodiment of the invention; and

FIG. 10 is a flow diagram illustrating a preferred method according to asecond embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

The embodiments of the invention and the various features andadvantageous details thereof are explained more fully with reference tothe non-limiting embodiments that are illustrated in the accompanyingdrawings and detailed in the following description. It should be notedthat the features illustrated in the drawings are not necessarily drawnto scale. Descriptions of well-known components and processingtechniques are omitted so as to not unnecessarily obscure theembodiments of the invention. The examples used herein are intendedmerely to facilitate an understanding of ways in which the embodimentsof the invention may be practiced and to further enable those of skillin the art to practice the embodiments of the invention. Accordingly,the examples should not be construed as limiting the scope of theembodiments of the invention.

As mentioned, there remains a need for a novel technique that allows foreasier and more precise inspections of damascene structures. Theembodiments of the invention achieve this need by providing a layer offluorescent or phosphorescent material into a damascene structure. Thelayer, which can easily be picked up under UV light and/or by slurryconcentration analysis, allows for easy in situ detection of residualliner defects and/or CMP endpoint detection. Referring now to thedrawings and more particularly to FIGS. 1 through 10 where similarreference characters denote corresponding features consistentlythroughout the figures, there are shown preferred embodiments of theinvention.

FIG. 1 illustrates an integrated circuit 5 embodied as a damascenestack, which comprises a substrate 10, which may comprise asingle-crystal silicon layer, or alternatively, the substrate 10 maycomprise any appropriate semiconducting material, including, but notlimited to silicon (Si), germanium (Ge), gallium phosphide (GaP), indiumarsenide (InAs), indium phosphide (InP), silicon germanium (SiGe),gallium arsenide (GaAs), or other semiconductors. Next, an interleveldielectric layer 20 is deposited over the substrate 10. The dielectriclayer 20 may comprise silicon oxide, FTEOS (silicon oxide with fluorineimpurities), Silk® (available from Dow Chemical Company, Midland, Mich.,USA), SiCOH (carbon-doped oxide), and with or without a hardmask layer(not shown). Next, a marker layer 30 is deposited on top of dielectriclayer 20. The marker layer 30 comprises a fluorescent or phosphorescentmaterial, such as phosphor, which is detectable upon exposing the markerlayer 30 to an ultraviolet light.

Next, as shown in FIG. 2, the damascene stack 5 is patterned using anytypical lithography and etching techniques known in the art, therebycreating a void 35 in the damascene stack 5. Then, as illustrated inFIGS. 3 and 4, the damascene stack 5 undergoes a metallization process,which involves the deposition of a liner 40 over all exposed surfaces ofthe damascene stack 5 including the exposed surfaces in the void 35. Theliner film 40 may comprise tungsten (W), titanium nitride (TiN) tantalum(Ta), and tantalum nitride (TaN). Thereafter, a plating metal 50, suchas copper (Cu) is deposited over the liner 40 thereby filling the void35.

The next step involves performing a CMP process on the metal layer 50and liner film 40 as shown in FIG. 5. The CMP is endpointed by using thephosphor concentration in the slurry (not shown). After endpoint, anoverpolishing process is performed. Alternatively, one may endpoint whenthe slurry is no longer fluorescing. The overpolishing process isdesigned to stop on the marker layer 30. At this point, the damascenestack 5 can be quickly examined with ultraviolet light (ray) to look forfluorescence or phosphorescence in the damascene stack 5 as indicated inFIG. 6. If there are areas with no fluorescence or phosphorescence, thenthis indicates that there is still residual metal 50 or liner 40 (i.e.,incomplete CMP) over the marker layer 30. If there remains residualmetal 50 or liner 40 over the marker layer 30, then the damascenestructure 5 (i.e., wafer) should be reworked with a touch up CMP processand can be re-examined. This process can continue until no residualmetal 50 or liner 40 remains over the marker layer 30.

FIG. 7 illustrates the process flow according to the first embodiment ofthe invention. FIG. 7 illustrates, with reference to FIGS. 1 through 6,a method of detecting whether post-CMP (chemical mechanical polishing)defects exist in an integrated circuit 5, wherein the method comprisesdepositing (101) a dielectric layer 20 over and adjacent to a substrate10; forming (103) a marker layer 30 over and adjacent to the dielectriclayer 20, wherein the marker layer 30 comprises an ultravioletdetectable material; patterning (105) the marker layer 30 and thedielectric layer 20 thereby creating exposed portions of the dielectriclayer 20; depositing (107) a liner 40 over and adjacent to the markerlayer 30 and the exposed portions of the dielectric layer 20; depositing(109) a metal layer 50 over and adjacent to the liner 40; polishing(111) the metal layer 50 and the liner 40; and exposing (113) the markerlayer 30 to an ultraviolet ray, wherein detection of the ultravioletdetectable material by the ultraviolet ray signals an absence of themetal layer 50 and the liner 40 over the marker layer 30. Additionally,the method further comprises re-polishing (115) the liner 40 uponnon-detection of the ultraviolet detectable material by the ultravioletray.

The method further comprises configuring the marker layer 30 as aseparate layer from the dielectric layer 20. In the step of forming(103) the marker layer 30, the ultraviolet detectable material comprisesfluorescent material or phosphorescent material. Furthermore, the markerlayer 30 signals an endpoint for CMP processing during fabrication ofthe integrated circuit 5. The method further comprises analyzingpolishing slurry effluent (not shown) generated from the polishingprocess (111) for a presence of the ultraviolet detectable material,wherein detection of the ultraviolet detectable material in thepolishing slurry effluent signals an endpoint for CMP processing duringfabrication of the integrated circuit 5. Alternatively, the methodfurther comprises analyzing polishing slurry effluent (not shown)generated from the polishing process (111) for an absence of theultraviolet detectable material, wherein non-detection of theultraviolet detectable material in the polishing slurry effluent signalsan endpoint for CMP processing during fabrication of the integratedcircuit 5.

A second embodiment of the invention is illustrated in FIGS. 8 through10. Generally, the first and second embodiments are similar up throughFIG. 4, which is the end of the metallization process. According to thesecond embodiment, the marker layer 30 does not act as a polishing stoplayer, but instead, is polished away completely as shown in FIG. 8. Thesudden presence or, alternatively, absence of phosphor in the slurry canalso be used as a reference point for endpointing the process. Accordingto the second embodiment, ultraviolet light is used to check for thepresence or absence of fluorescence or phosphorescence, as illustratedin FIG. 9. Accordingly, if some of the liner 40 and marker layer 30residuals remain after the CMP process in the area above the dielectriclayer 20, then there will be a thickness variation from the areas withexposed residuals to the areas with the exposed marker layer 30 to theareas with the exposed dielectric layer 20. In other words, iffluorescence or phosphorescence is seen above the dielectric layer 20,then it is indicative of there being metal 50 or liner 40 residuals,which necessitates an additional CMP process to remove the remainingresidual materials.

FIG. 10 illustrates the process flow according to the second embodimentof the invention. FIG. 10 illustrates, with reference to FIGS. 1 through4 and FIGS. 8 and 9, a method of detecting whether post-CMP (chemicalmechanical polishing) defects exist in an integrated circuit 5, whereinthe method comprises depositing (201) a dielectric layer 20 over andadjacent to a substrate 10; forming (203) a marker layer 30 comprisingan ultraviolet detectable material over and adjacent to the dielectriclayer 20; patterning (205) the marker layer 30 and the dielectric layer20 thereby creating exposed portions of the dielectric layer 20;depositing (207) a liner 40 over the marker layer 30; depositing (209) ametal layer 50 over and adjacent to the liner 40; and polishing (211)the metal layer 50, the liner 40, and the marker layer 30. The methodfurther comprises exposing (213) the dielectric layer 20 to anultraviolet light, and detecting (215) whether the liner 40 and themarker layer 30 are present over the dielectric layer 20, whereindetection of the ultraviolet detectable material by the ultravioletlight signals a presence of the liner 40 and the marker layer 30 overthe dielectric layer 20. Furthermore, the method comprises re-polishing(217) the liner 40 and the marker layer 30 upon detection of theultraviolet detectable material by the ultraviolet light.

As with the first embodiment, the method according to the secondembodiment further comprises configuring the marker layer 30 as aseparate layer from the dielectric layer 20. In the step of forming(203) the marker layer 30, the ultraviolet detectable material comprisesfluorescent material or phosphorescent material. Additionally, themethod according to the second embodiment further comprises analyzingpolishing slurry effluent (not shown) generated from the polishingprocess for a presence or, alternatively, an absence of the ultravioletdetectable material, wherein detection or, alternatively, non-detectionof the ultraviolet detectable material in the polishing slurry effluentsignals an endpoint for CMP processing during fabrication of theintegrated circuit 5.

The detection method provided by the embodiments of the invention isintended to determine whether metal 50 or liner 40 materials remain onlyover the marker layer 30. As illustrated in FIGS. 1 through 6 and 8through 9, the liner 40 will remain in the integrated circuit 5 in areasprotected by the metal layer 50, which are generally referred to as the“damascene” regions of the integrated circuit 5. It is in the“non-damascene” regions where shorting can occur if liner 40 or metal 50remains, as such, it is in the “non-damascene” regions where theultraviolet detection occurs.

The advantages afforded by the embodiments of the invention includeimproved process yield, performance, and reliability. Moreover, theembodiments of the invention also provide a low-cost improvement, whichmay reduce overall processing time by limiting the number of rework orCMP “touch-up” steps. By monitoring the CMP slurry for lack of markermaterial after the marker material is first detected, overpolishing ofthe damascene lines (which would result in higher resistance wires) canalso be reduced.

The foregoing description of the specific embodiments will so fullyreveal the general nature of the invention that others can, by applyingcurrent knowledge, readily modify and/or adapt for various applicationssuch specific embodiments without departing from the generic concept,and, therefore, such adaptations and modifications should and areintended to be comprehended within the meaning and range of equivalentsof the disclosed embodiments. It is to be understood that thephraseology or terminology employed herein is for the purpose ofdescription and not of limitation. Therefore, while the invention hasbeen described in terms of preferred embodiments, those skilled in theart will recognize that the embodiments of the invention can bepracticed with modification within the spirit and scope of the appendedclaims.

1. An integrated circuit comprising: a substrate; a dielectric layerover said substrate; a marker layer over said dielectric layer; a linerover said marker layer and said dielectric layer; and a metal layer oversaid liner, wherein said marker layer comprises an ultravioletdetectable material, which upon excitation by an ultraviolet ray signalsan absence of said metal layer and said liner over said marker layer. 2.The integrated circuit of claim 1, wherein said marker layer comprises aseparate layer from said dielectric layer.
 3. The integrated circuit ofclaim 1, wherein said ultraviolet detectable material comprisesfluorescent material.
 4. The integrated circuit of claim 1, wherein saidultraviolet detectable material comprises phosphorescent material.
 5. Anintegrated circuit comprising: a substrate; a dielectric layer adjacentto said substrate; a marker layer adjacent to said dielectric layer,wherein said marker layer comprises a separate layer from saiddielectric layer; a liner adjacent to said marker layer and saiddielectric layer; and a metal layer adjacent to said liner, wherein saidmarker layer comprises an ultraviolet detectable material, which uponexcitation by an ultraviolet ray signals an absence of said metal layerand said liner over said marker layer.
 6. The integrated circuit ofclaim 5, wherein said ultraviolet detectable material comprisesfluorescent material.
 7. The integrated circuit of claim 5, wherein saidultraviolet detectable material comprises phosphorescent material.
 8. Anintegrated circuit comprising: a substrate; a dielectric layer over saidsubstrate; a marker layer over said dielectric layer; a liner over saidmarker layer and said dielectric layer; and a metal layer over saidliner.
 9. The integrated circuit of claim 8, wherein said marker layercomprises a separate layer from said dielectric layer.
 10. Theintegrated circuit of claim 8, wherein said ultraviolet detectablematerial comprises fluorescent material.
 11. The integrated circuit ofclaim 8, wherein said ultraviolet detectable material comprisesphosphorescent material.